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[Other resource] 8stepSymmetryCoefficientFilter

Description: 8阶对称系数并行FIR滤波器(verilog)用作数字滤波，系数可调。根据实际截止频率决定。
Platform: | Size: 1146 | Author: TGY | Hits:

[Other resource] fpga

Description: fpga功能实现有限字长响应FIR 用verilog编写
Platform: | Size: 138914 | Author: 吴务 | Hits:

[Other resource] FIR_verilog

Description: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形
Platform: | Size: 628941 | Author: yejianchao | Hits:

[Communication-Mobile] suAra6Rm

Description: fir滤波器的Verilog程序,看看吧，还不错！
Platform: | Size: 4518 | Author: wanghua | Hits:

[Other resource] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真
Platform: | Size: 24408 | Author: 宇天 | Hits:

[Communication-Mobile] DDC

Description: 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR-DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
Platform: | Size: 2048 | Author: yeong | Hits:

[Windows Develop] atribute_fir

Description: 分布式的FIR的verilog功能代码编写,该FIR为四阶的典型功能描述!-verilog
Platform: | Size: 560128 | Author: 阮开明 | Hits:

[VHDL-FPGA-Verilog] base_fir

Description: 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
Platform: | Size: 21504 | Author: xiaoLEE | Hits:

[DSP program] fir8

Description: 用verilog编写的8阶串行fir滤波器-verilog vhdl fir
Platform: | Size: 1024 | Author: 2000flash | Hits:

[Other] da_fir

Description: 分布式FIR程序Verilog语言，数字滤波器设计-DAfir
Platform: | Size: 2072576 | Author: 吴知 | Hits:

[Embeded-SCM Develop] firfilterverilog

Description: 用VERILOG语言实现的FIR数字滤波器-VERILOG language with the FIR digital filter
Platform: | Size: 243712 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] verilogFir

Description: 基于Verilog+HDL的FIR数字滤波器设计与仿真 -Verilog+ HDL based on the FIR digital filter design and simulation
Platform: | Size: 167936 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 使用Verilog编程实现的分布式FIR滤波器源码，经过调试能够完成功能-Distributed programming using the Verilog source code FIR filters, after a debugging feature to complete
Platform: | Size: 14336 | Author: lisa1027 | Hits:

[Embeded-SCM Develop] a

Description: 个人整理的关于FIR滤波器、加法器、减法器的verilog程序，供大家下载-It’s about some programs about filter，and some others I‘ll be happy if it s better for you~~~
Platform: | Size: 4096 | Author: SkySeraph | Hits:

[Communication-Mobile] firVerilog

Description: 用verilog语言编写的一个FIR滤波器的程序-Verilog language with a FIR filter process
Platform: | Size: 4096 | Author: 夏宝平 | Hits:

[VHDL-FPGA-Verilog] verilogFIR

Description: 本源码为Verilog的FIR数字滤波器 测试后性能很不错的-The source of the FIR digital filter for the Verilog test performance is very good
Platform: | Size: 638976 | Author: 123 | Hits:

[Program doc] firfilter14

Description: 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
Platform: | Size: 2048 | Author: 卢大成 | Hits:

[VHDL-FPGA-Verilog] fir_srg

Description: 该程序是利用Verlag HDL硬件描述语言实现的fir数字滤波器，希望对刚学习verilog的朋友有所帮助。-The procedure is to use Verlag HDL hardware description language implementation of fir digital filters, just want to help a friend learn verilog.
Platform: | Size: 1024 | Author: 孙科 | Hits:

[VHDL-FPGA-Verilog] ser_fir

Description: 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
Platform: | Size: 1024 | Author: hgdlsl | Hits:

[VHDL-FPGA-Verilog] FIR_chanbing

Description: 串并结构的FIR滤波器,Verilog语言编写，希望对大家有帮助-String and the structure of FIR filter, Verilog language, we want to help
Platform: | Size: 13312 | Author: | Hits:
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